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gs8182s18d-200/167 18mb burst of 2 ddr sigmasio-ii sram 200 mhz?167 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.09 7/2006 1/30 ? 2003, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? dll circuitry for wide output data valid window and future frequency scaling ? burst of 2 read and write ? 1.8 v +150/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq mode pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 13 mm x 15 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available ? pin-compatible with future 36mb, 72mb, and 144mb devices sigmaram ? family overview gs8182s18 are built in compli ance with the sigmasio-ii sram pinout standard for separate i/o synchronous srams. they are 18,874,368-bit (18mb) sr ams. these are the first in a family of wide, very low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. clocking and addressing schemes a burst of 2 sigmasio-ii sram is a synchronous device. it employs dual input register clock inputs, k and k . the device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, c and c . if the c clocks are tied high, the k clocks are routed internally to fire the ou tput registers instead. each burst of 2 sigmasio-ii sram also supplies echo clock outputs, cq and cq , which are synchronized with read data output. when used in a source synchronous clocking scheme, the echo clock outputs can be used to fire input registers at the data?s destination. because separate i/o burst of 2 rams always transfer data in two packets, a0 is internally set to 0 for the first read or write transfer, and automatically in cremented by 1 for the next transfer. because the lsb is tie d off internally, the address field of a burst of 2 ram is always one address pin less than the advertised index depth (e.g., the 1m x 18 has a 512k addressable index). parameter synopsis -200 -167 tkhkh 5.0 ns 6.0 ns tkhqv 0.45 ns 0.5 ns 165-bump, 13 mm x 15 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view jedec std. mo-216, variation cab-1
1m x 18 sigmaquad sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq v ss /sa (144mb) nc/sa (36mb) r/ w bw1 k nc ld sa v ss /sa (72mb) cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h d off v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 2/30 ? 2003, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r/ w synchronous read/ write input bw0 ? bw1 synchronous byte writes input active low k input clock input active high c output clock input active high tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? k input clock input active low c output clock output active low d off dll disable ? active low ld synchronous load pin ? active low cq output echo clock output active low cq output echo clock output active high d synchronous data inputs input q synchronous data outputs output v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 or 1.5 v nominal v ss power supply: ground supply ? notes: 1. c, c , k, or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd , output impedance is set to minimum value and it cannot be connected to ground or left uncon - nected. 3. nc = not connected to die or any other pin gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 3/30 ? 2003, gsi technology background separate i/o srams, like sigmaquad srams, are attractive in ap plications where alternating read s and writes are needed. on the other hand, common i/o srams like the sigmacio family are popula r in applications where bursts of read or write traffic are needed. the sigmasio sram is a hybrid of these two devices. like the sigmaq uad family devices, the sigmasio features a separate i/o data path, offering the user independent data in and data out pins. however, the sigmasio devices offer a control protocol like that offered on the sigmacio devices. therefore, while sigmaquad srams allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. sigmasio srams allow continuous loads of read or write addresses like sigmacio srams, but in a separate i/o configuration.
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 4/30 ? 2003, gsi technology like a sigmaquad sram, a sigmasio-ii sram can execute an alternating sequence of reads and writes. however, doing so results in the data in port and the data out port stalling with nothing to do on alternate transfers. a sigmaquad device would keep both ports running at capacity full time. on the other hand, th e sigmasio device can accept a continuous stream of read command s and read data or a continuous stream of write commands and wr ite data. the sigmaquad device, by contrast, restricts the user fr om loading a continuous stream of read or wr ite addresses. the advantage of the sigmasio device is that it allows twice the random address bandwidth for either reads or writ es than could be acheived with a sigmaqua d version of the device. sigmacio srams offer this same advantage, but do not have the separate data in and data out pins offered on the sigmasio srams. therefore, sigmasio devices are useful in psuedo dual port sram a pplications where communication of burst traffic between two electrically independent busses is desired. each of the three sigmaquad family sra ms?sigmaquad, sigmacio, an d sigmasio?supports similar address rates because random address rate is determined by the internal performance of the ram. in addition, all th ree sigmaquad family srams are based on the same internal circuits. differ ences between the truth tables of the diff erent devices proceed from differences in how the ram?s interface is contrived to interact with the rest of the system. each mode of operation has its own advantages and disadvantages. the user should cons ider the nature of the work to be done by the ram to evaluate which version is best suited t o the application at hand. burst of 2 sigmasio-ii sram ddr read the status of the address input, r/ w , and ld pins are sampled at each rising edge of k. ld high causes chip disable. a high on the r/ w pin begins a read cycle. data can be clocked out af ter the next rising edge of k with a rising edge of c (or by k if c and c are tied high), and after the following rising edge of k with a rising edge of c (or by k if c and c are tied high). sigmasio-ii double data rate sram read first read a write b read c write d nop read e read f nop a b c d e f b b+1 d d+1 b b+1 d d+1 a a+1 c c+1 e e+1 f k k address ld r/w bwx d c c q cq cq
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 5/30 ? 2003, gsi technology burst of 2 sigmasio-ii sram ddr write the status of the address input, r/ w , and ld pins are sampled at each rising edge of k. ld high causes chip disable. a low on the r/ w pin, begins a write cycle. data is clocked in by the next rising edge of k and then the rising edge of k . sigmasio-ii double data rate sram write first write a read b nop read c write d nop read e read f nop a b c d e f a a+1 d d+1 a a+1 d d+1 b b+1 c c+1 e e+1 f k k address ld r/w bwx d c c q cq cq
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 6/30 ? 2003, gsi technology special functions byte write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. a ny or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write addres s loaded into the ram provides the base ad dress for a 2 beat data transfer. the x18 version of the ram, for example, may write 36 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in resulting write operation beat 1 beat 2 d0?d8 d9?d17 d0?d8 d9?d17 written unchanged unchanged written output register control sigmasio-ii srams offer two mechanisms for controlling the output data registers. typically, control is handled by the output register clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of th e k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs.
a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 d a k w d a k w d a k w d r r r qqq q cc cc q 1 ?q n c w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn is not shown. cq cq cq cq cq 0 cq 1 cq 2 cq 3 gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 7/30 ? 2003, gsi technology example four bank depth expansion schematic
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 8/30 ? 2003, gsi technology burst of 2 sigmasio-ii sram depth expansion write a read b write c read d write e read f read g read h nop a b c d e f g h a a+1 e e+1 c c+1 a a+1 e e+1 c c+1 d d+1 g b b+1 f f+1 k k address ld (bank_1) ld (bank_2) r/w (bank_1) r/w (bank_2) bwx (bank_1) bwx (bank_2) d(bank_1) d(bank_2) c(bank_1) c (bank_1) q(bank_1) cq(bank)1 cq (bank_1) c(bank_2) c (bank_2) q(bank_2) cq(bank_2) cq (bank_2) flxdrive-ii output driver impedance control hstl i/o sigmasio-ii srams are supplied with programmable impe dance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow the sram to monitor and adju st its output driver impedance. the value of rq must be 5x t he value of the intended line impedance driven by the sram. the allowable range of rq to guar antee impedance matching with a vendor-specified tolerance is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. the sram?s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. a clock cy cle counter periodically triggers an impedance evaluation, rese ts and counts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps.
separate i/o burst of 2 si gmasio-ii sram truth table a ld r/ w current operation d d q q k (t n ) k (t n ) k (t n ) k (t n ) k (t n+1 ) k (t n+1 ) k (t n+1 ) k (t n+1 ) x 1 x deselect x ? hi-z ? v 0 1 read x ? q0 q1 v 0 0 write d0 d1 hi-z ? notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?v ? = input ?valid?; ?x? = input ?don?t care? 2. ??? indicates that the input requirement or output state is determined by the next operation. 3. q0 and q1 indicate the first and second pieces of output data transferr ed during read operations. 4. d0 and d1 indicate the first and second pieces of input data transferred during write operations. 5. qs are tristated for one cycle in response to deselect and wr ite commands, one cycle after the command is sampled, except whe n pre - ceded by a read command. 6. cq is never tristated. 7. users should not clock in metastable addresses. gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 9/30 ? 2003, gsi technology
x18 byte write clock truth table bw bw current operation d d k (t n+1 ) k (t n+2 ) k (t n ) k (t n+1 ) k (t n+2 ) t t write dx stored if bwn = 0 in both data transfers d1 d2 t f write dx stored if bwn = 0 in 1st data transfer only d1 x f t write dx stored if bwn = 0 in 2nd data transfer only x d2 f f write abort no dx stored in either data transfer x x notes: 1. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. 2. if one or more bwn = 0, then bw = ?t?, else bw = ?f?. x18 byte write enable ( bwn ) truth table bw1 bw0 d9?d17 d0?d8 1 1 don?t care don?t care 0 1 don?t care data in 1 0 data in don?t care 0 0 data in data in gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 10/30 ? 2003, gsi technology
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 11/30 ? 2003, gsi technology state diagram power-up nop load new address ddr read ddr write read load write load load load load load
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.3 ( note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 12/30 ? 2003, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.5 v i/o supply voltage v ddq 1.4 1.5 1.65 v 1 1.8 v i/o supply voltage v ddq 1.7 1.8 1.95 v 1 reference voltage v ref 0.68 ? 0.95 v 1 notes: 1. unless otherwise noted, all perfo rmance specifications quoted are evaluated for worst case at both 1.4 v , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 13/30 ? 2003, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 0.1 v ddq + 0.3 mv 1 dc input logic low v il (dc) ?0.3 v ref ? 0.1 mv 1 note: compatible with both 1.8 v and 1.5 v i/o drivers hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 0.2 ? mv 3,4 ac input logic low v il (ac) ? v ref ? 0.2 mv 3,4 v ref peak to peak ac voltage v ref (ac) ? 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers . compatible with both 1.8 v and 1.5 v i/o drivers. 4. see ac input definition drawing below. v ih (ac) v ref v il (ac) hstl i/o ac input definitions 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il
capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf note: this parameter is sample tested. gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 14/30 ? 2003, gsi technology ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25 = 3.3 v)
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 15/30 ? 2003, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 ? rq 350 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? rq 350 ?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v 4. minimum impedance mode, zq = v ss 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter org symbol -200 -167 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x18 idd 410 ma 420 ma 365 ma 375 ma v dd =max.; i out = 0 ma; cycle time t khkh min. standby current (nop) x18 isb1 200 ma 205 ma 195 ma 200 ma device deselected; i out = 0 ma; f = max; all inputs 0.2 v or v dd ? 0.2 v notes: 1. power measured with output pins floating. 2. all inputs (except zq, v ref ) are held at either v ih or v il . 3. operating supply currents are measured at 100% buss utilization. 4. nop currents are valid when entering nop after all pending read and write cycles are completed.
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 16/30 ? 2003, gsi technology ac electrical characteristics parameter symbol -200 -167 units notes min max min max clock k, k clock cycle time c, c clock cycle time t khkh t chch 5.0 7.88 6.0 8.4 ns ttkc variable t kcvar ? 0.2 ? 0.2 ns 5 k, k clock high pulse width c, c clock high pulse width t khkl t chcl 2.0 ? 2.4 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 2.0 ? 2.4 ? ns k to k high c to c high t kh kh 2.3 ? 2.8 ? ns k, k clock high to c, c clock high t khch 0 2.3 0 2.8 ns dll lock time t kclock 1024 ? 1024 ? cycle 6 k static to dll reset t kcreset 30 ? 30 ? ns output times k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 0.45 ? 0.5 ns 3 k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx ?0.45 ? ?0.5 ? ns 3 k, k clock high to echo clock valid c, c clock high to echo clock valid t khcqv t chcqv ? 0.45 ? 0.5 ns k, k clock high to echo clock hold c, c clock high to echo clock hold t khcqx t chcqx ?0.45 ? ?0.5 ? ns cq, cq high output valid t cqhqv ? 0.35 ? 0.40 ns 7 cq, cq high output hold t cqhqx ?0.35 ? ?0.40 ? ns 7 k clock high to data output high-z c clock high to data output high-z t khqz t chqz ? 0.45 ? 0.5 ns 3 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 ?0.45 ? ?0.5 ? ns 3 setup times address input setup time t avkh 0.6 ? 0.7 ? ns control input setup time t ivkh 0.6 ? 0.7 ? ns 2 data input setup time t dvkh 0.4 ? 0.5 ? ns
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 17/30 ? 2003, gsi technology k controlled read-first timing diagram read a write b read c read e deselect deselect a b c d e b b+1 b b+1 a a+1 c c+1 d d+1 cqhqx cqhqv khcqv khcqx khqx khqv khqz khqx1 khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh kh#kh klkhklkh khklkhkl khkhkhkh k k address ld r/w bwx d q cq cq hold times address input hold time t khax 0.6 ? 0.7 ? ns control input hold time t khix 0.6 ? 0.7 ? ns data input hold time t khdx 0.4 ? 0.5 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r , w , bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 3. if c, c are tied high, k, k become the references for c, c timing parameters 4. to avoid bus contention, at a given vo ltage and temperature tchqx1 is bigger than tc hqz. the specs as shown do not imply bus conten - tion because tchqx1 is a min parameter that is wo rst case at totally different test conditions (0 c, 1.9 v) than tchqz, which is a max parameter (worst case at 70 c, 1.7 v). it is not possible for two srams on the same board to be at such different voltages and tempera - tures. 5. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 6. v dd slew rate must be less than 0.1 v dc per 50 ns fo r dll lock retention. dll lock time begins once v dd and input clock are stable. 7. echo clock is very tightly controlled to data valid/data hold. by design, there is a 0.1 ns variation from echo clock to dat a. the datasheet parameters reflect tester guard bands and test setup variations. ac electrical character istics (continued) parameter symbol -200 -167 units notes min max min max
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 18/30 ? 2003, gsi technology k controlled write- first timing diagram nop write a read b read c write d write e deselect a b c d e a a+1 d d+1 e e+1 a a+1 d d+1 e e+1 b b+1 c c+1 cqhqx cqhqv khcqv khcqx khcqv khcqx khqz khqv khqx khqx1 khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh kh#kh klkhklkh khklkhkl khkhkhkh k k address ld r/w bwx d q cq cq
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 19/30 ? 2003, gsi technology c controlled read-first timing diagram read a write b read c read d deselect deselect a b c d b b+1 b b+1 a a+1 c c+1 d d+1 cqhqx cqhcv chcqv chcqx chqx chqv chqz chqx1 chch# chchchch clchclch chclchcl khch khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkh# klkhklkh khkl khkh khkl khkh k k address ld r/w bwx d c c q cq cq
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 20/30 ? 2003, gsi technology c controlled write- first timing diagram nop write a read b write c write d read e deselect a b c d e a a+1 c c+1 d d+1 a a+1 c c+1 d d+1 b b+1 cqhqx cqhqv chqz chqv chqx chqx1 kh#kh klkhklkh khklkhkl khkhkhkh khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh kh#kh klkhklkh khklkhkl khkhkhkh k k addr ld r/w bwx d c c q cq cq
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 21/30 ? 2003, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible.
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 22/30 ? 2003, gsi technology boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins.
id register contents not used gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1 gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 23/30 ? 2003, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandator y for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table.
select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 24/30 ? 2003, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins.
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 25/30 ? 2003, gsi technology typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 26/30 ? 2003, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.6 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < vi < v ddn +1 v not to exceed v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj ddn 3. 0 v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 27/30 ? 2003, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns
gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 28/30 ? 2003, gsi technology package dimensions?165-b ump fpbga (package d) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.05 150.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.40 max.
ordering information?gsi sigmasio-ii sram org part number 1 type package speed (mhz) t a 2 status 3 1m x 18 gs8182s18d-200 sigmasio-ii sram 165-pin bga 200 c mp 1m x 18 gs8182s18d-167 sigmasio-ii sram 165-pin bga 167 c mp 1m x 18 gs8182s18d-200i sigmasio-ii sram 165-pin bga 200 i mp 1m x 18 gs8182s18d-167i sigmasio-ii sram 165-pin bga 167 i mp 1m x 18 gs8182s18gd-200 sigmasio-ii sram rohs-compliant 165-pin bga 200 c mp 1m x 18 gs8182s18gd-167 sigmasio-ii sram rohs-compliant 165-pin bga 167 c mp 1m x 18 gs8182s18gd-200i sigmasio-ii sram rohs-compliant 165-pin bga 200 i mp 1m x 18 GS8182S18GD-167I sigmasio-ii sram rohs-compliant 165-pin bga 167 i mp notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs8182s18d-200t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range. 3. mp = mass production. pq = pre-qualification. gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 29/30 ? 2003, gsi technology
sigmasio-ii revision history file name format/content description of changes 8182sxx_r1 creation of datasheet 8182sxx_r1; 8182sxx_r1_01 content ? changed 330 mhz to 333mhz ? removed any references to 133 mhz or 100 mhz 8182sxx_r1_01; 8182sxx_r1_02 content ? updated ac spec information 8182sxx_r1_02; 8182sxx_r1_03 content ? comprehensive rewrite, including (but not limited to) tables, pinouts, and timing diagrams 8182sxx_r1_03; 8182sxx_r1_04 content ? removed x36 configuration ? removed 333 and 300 mhz speed bins ? updated format 8182sxx_r1_04; 8182sxx_r1_05 content ? updated timing diagrams ? corrected erroneous vdd information in pin description table ? deleted erroneous sentent in flxdrive section 8182sxx_r1_05; 8182sxx_r1_06 content ? added 165 bga pb-free information ? added storage under bias information ? incorporated idd information into operating currents table ? updated test conditions for operating currents table ? added max numbers for tkhkh and tchch in ac char. table ? added clock to /clock delay timing to ac char. table 8182sxx_r1_06; 8182sxx_r1_07 content ? updated timing diagrams 8182sxx_r1_07; 8182sxx_r1_08 content ? added 267 mhz speed bin 8182sxx_r1_08; 8182sxx_r1_09 content ? updated datasheet for mp qualification ? removed 267 and 250 mhz speed bins gs8182s18d-200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.09 7/2006 30/30 ? 2003, gsi technology

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